Flip-flops and latches are basic memory elements used in digital electronics, computer engineering, and control systems. This cheat sheet helps students compare common device types, read timing diagrams, and choose the right storage element for a circuit. It is useful for understanding registers, counters, state machines, and sequential logic design.
A latch is level-sensitive, while a flip-flop is edge-triggered. The most important ideas are present state Q, next state Q(next), inputs, clock behavior, setup time, hold time, and propagation delay. Core devices include SR, D, JK, and T types, each with a truth table or characteristic equation that predicts the next output.
Key Facts
- A latch is level-sensitive, so it can change output while its enable input is active.
- A flip-flop is edge-triggered, so it changes output only on the specified rising or falling clock edge.
- For a D latch or D flip-flop, Q(next) = D when the device is transparent or clocked.
- For an SR latch with active-high inputs, S = 1 and R = 0 sets Q to 1, while S = 0 and R = 1 resets Q to 0.
- For an active-high SR latch, S = 1 and R = 1 is invalid because it can force both outputs into a noncomplementary or unstable condition.
- For a JK flip-flop, J = 0 and K = 0 holds, J = 1 and K = 0 sets, J = 0 and K = 1 resets, and J = 1 and K = 1 toggles.
- For a T flip-flop, Q(next) = Q when T = 0 and Q(next) = not Q when T = 1.
- A timing path is reliable only when data is stable before the clock for setup time and after the clock for hold time.
Vocabulary
- Latch
- A latch is a level-sensitive memory circuit that stores one bit and can change output while its enable signal is active.
- Flip-flop
- A flip-flop is an edge-triggered memory circuit that stores one bit and changes output only at a clock edge.
- Clock edge
- A clock edge is the transition of a clock signal from low to high or high to low that triggers a flip-flop.
- Setup time
- Setup time is the minimum time the input data must be stable before the triggering clock edge.
- Hold time
- Hold time is the minimum time the input data must remain stable after the triggering clock edge.
- Propagation delay
- Propagation delay is the time between an input or clock change and the resulting output change.
Common Mistakes to Avoid
- Treating a latch like an edge-triggered flip-flop is wrong because a latch can keep changing while enable is active, which may cause unintended output changes.
- Using S = 1 and R = 1 on an active-high SR latch is wrong because that input combination is invalid and can create unpredictable behavior.
- Ignoring setup time is wrong because data that changes too close to the clock edge may not be captured correctly.
- Ignoring hold time is wrong because data that changes immediately after the clock edge can corrupt the stored value.
- Confusing JK toggle behavior with D behavior is wrong because JK with J = 1 and K = 1 toggles, while a D flip-flop simply copies D at the clock edge.
Practice Questions
- 1 A positive-edge D flip-flop has D = 1 just before the rising clock edge. What is Q after the propagation delay?
- 2 A JK flip-flop currently has Q = 0. If J = 1 and K = 1 at the active clock edge, what is Q(next)?
- 3 A T flip-flop starts at Q = 1 and receives four active clock edges while T = 1. What is the final value of Q?
- 4 Explain why a designer might choose an edge-triggered flip-flop instead of a level-sensitive latch in a synchronous digital circuit.
Understanding Flip-Flops & Latches Reference
Memory in a digital circuit comes from feedback. Part of the output is fed back into the input logic, so the circuit can keep a value after an input pulse ends. This is different from a simple logic gate, whose output depends only on its current inputs.
In a storage element, the old output is part of the decision about the new output. This feedback must be designed carefully.
If two competing paths change at nearly the same time, the circuit may briefly behave in an unpredictable way. The SR circuit shows this clearly because its forbidden input case asks the circuit to set and reset itself at once.
Clocking gives a large circuit an agreed rhythm. A processor may contain millions or billions of storage elements, so it needs a way to move data in controlled steps. Combinational logic works between clock events.
A register captures the result at an event, then holds it steady while the next block of logic works. This separation makes complex designs manageable. In a timing diagram, follow one clock edge at a time.
Identify the value at the input just before that edge, then account for propagation delay before expecting the output to change. The output does not usually move at the exact instant of the edge.
Setup time and hold time describe a small protected interval around a clock edge. Data must arrive early enough for the internal circuit to recognize it. It must remain unchanged long enough for the stored value to settle.
If either rule is broken, a flip-flop can enter metastability. Its output may take longer than normal to become a clear zero or one. Metastability cannot be fully removed when an external signal arrives without the clock's timing relationship.
Designers reduce the risk by passing such signals through two flip-flops in sequence. This is common for push buttons, sensor signals, and data arriving from another clock domain.
Different storage types fit different jobs. D flip-flops are widely used in registers because one data input makes the intended next value easy to see. T flip-flops are useful in counters because each active input event can reverse the stored bit.
Several toggle stages can divide a clock frequency, though the outputs of a simple ripple counter do not all change together. JK flip-flops avoid the forbidden SR condition and can model several behaviors, but they are less common in many modern programmable designs. When studying truth tables, do not memorize rows alone.
Start with the current value, apply the inputs at the correct time, then write the next value. This method makes state tables, counters, and finite state machines much easier to trace.
Real circuits need more than correct logic equations. A button can bounce between zero and one many times when pressed. A long wire can pick up noise.
A reset signal may need special handling during power up. A circuit may work in a slow simulation yet fail in hardware if its clock is too fast for the available logic delay.
Check whether a reset is synchronous or asynchronous, whether a clock edge is rising or falling, and whether signals cross between unrelated clocks. These details often explain errors that a truth table alone cannot show.