Sequential logic circuits store information and change output based on both current inputs and past states. This cheat sheet helps engineering students organize the key ideas behind flip-flops, registers, and counters. It is useful when reading timing diagrams, designing state machines, or checking whether a circuit will count correctly.
Students need these rules because small timing errors can cause incorrect states in real digital systems.
The core idea is that a clock controls when stored bits update. Flip-flops hold one bit, registers hold groups of bits, and counters move through a planned sequence of binary states. State tables, excitation tables, and timing diagrams show how a circuit behaves from one clock edge to the next.
Important timing limits include propagation delay, setup time, hold time, and maximum clock frequency.
Key Facts
- A sequential circuit has memory, so its output depends on present inputs and the present state stored in flip-flops.
- A D flip-flop copies its input on the active clock edge, so Q(next) = D.
- A T flip-flop toggles when T = 1 and holds when T = 0, so Q(next) = Q when T = 0 and Q(next) = not Q when T = 1.
- A JK flip-flop holds for JK = 00, resets for JK = 01, sets for JK = 10, and toggles for JK = 11.
- An n-bit binary counter has 2^n possible states, so a 4-bit counter can represent 16 states from 0000 to 1111.
- For a mod-N counter, the circuit repeats after N states, and the minimum number of flip-flops is the smallest n such that 2^n >= N.
- Setup time means the input must be stable for at least t_setup before the active clock edge, and hold time means it must remain stable for at least t_hold after the edge.
- A safe maximum clock frequency can be estimated by f_max = 1 / (t_clk-to-Q + t_logic + t_setup), using the longest combinational path between flip-flops.
Vocabulary
- Sequential logic
- A type of digital logic in which outputs depend on current inputs and stored past information.
- Flip-flop
- A clocked memory element that stores one binary bit, usually labeled Q.
- Clock edge
- The rising or falling transition of a clock signal that triggers a state update in edge-triggered circuits.
- State table
- A table that lists each present state, input condition, next state, and output for a sequential circuit.
- Counter
- A sequential circuit that moves through a fixed sequence of states, often representing binary numbers.
- Propagation delay
- The time between a change at a circuit input or clock edge and the resulting stable change at the output.
Common Mistakes to Avoid
- Confusing combinational logic with sequential logic is wrong because sequential logic includes stored state, so the same input can produce different outputs at different times.
- Ignoring setup and hold time is wrong because a flip-flop may enter an unstable or incorrect state if its input changes too close to the clock edge.
- Using too few flip-flops for a counter is wrong because n flip-flops can only represent 2^n states, so a mod-10 counter needs at least 4 flip-flops.
- Reading a ripple counter like a synchronous counter is wrong because ripple counter outputs do not all change at the same instant and can briefly show invalid states.
- Resetting a mod-N counter at the wrong state is wrong because the counter may skip a needed state or include an extra unwanted state in the count sequence.
Practice Questions
- 1 How many flip-flops are needed to build a mod-12 counter, and how many unused states will exist?
- 2 A 3-bit binary counter starts at 000 and receives five active clock edges. What is the final count?
- 3 A synchronous path has t_clk-to-Q = 3 ns, t_logic = 12 ns, and t_setup = 2 ns. Estimate the maximum clock frequency.
- 4 Explain why a synchronous counter is usually preferred over a ripple counter in a high-speed digital system.
Understanding Sequential Logic & Counters Reference
A useful way to understand a sequential circuit is to separate its storage part from its decision part. Flip-flops store the current state. Combinational logic examines that state together with external inputs, then produces the values that will be stored at the next clock event.
This creates a repeated cycle of observe, calculate, store. A reset signal gives the circuit a known starting state.
Without a reliable reset, a counter or state machine may begin in any allowed state after power is applied. Designers often choose reset states carefully because the first few actions of a device can depend on them.
Real flip-flops do not make an instant, perfectly clean decision. Near a clock edge, an input that changes too close to the edge can leave the internal circuit temporarily uncertain. This condition is called metastability.
Its output may settle to zero or one after an unpredictable delay. Metastability cannot be completely removed when a signal comes from outside the clocked system, such as a push button, sensor, or another clock domain.
Engineers reduce the risk by passing such signals through synchronizer flip-flops. A mechanical button needs another step called debouncing because one press can create many rapid electrical transitions.
Counters come in two main timing styles. In a ripple counter, one flip-flop output clocks the next flip-flop. This uses little logic, but each bit changes after the previous bit changes.
During a transition, the outputs can briefly show unwanted intermediate values. A decoder connected to those outputs may react to a false value. In a synchronous counter, every flip-flop receives the same clock.
Logic determines which bits change at each edge, so the count is more predictable. Synchronous designs are usually preferred when a counter feeds displays, memory addresses, control logic, or other fast circuits.
A mod counter may have unused binary states. Good designs force an unused state back into the intended sequence.
Timing analysis follows data from one flip-flop to the next. After the first flip-flop receives a clock edge, its output needs clock to Q delay before it changes. The signal then travels through gates, wires, and possibly several logic blocks.
It must arrive early enough to meet the setup requirement of the receiving flip-flop. The longest route limits the clock rate. The basic estimate says maximum frequency equals one divided by clock to Q delay plus logic delay plus setup time.
Hold time checks the opposite problem. Data must not arrive too soon after the same clock edge.
Lowering the clock frequency can help a setup failure, but it does not fix a hold failure. Hold failures often need added delay or a change to the physical routing.
When reading a timing diagram, mark each active clock edge first. Then decide which input values are valid at that edge. Update the stored state only after considering the flip-flop delay, not at random points between edges.
For state tables, write the present state, input condition, next state, and required outputs in a consistent order. Check every possible state, including ones the intended counter never normally reaches.
Students often lose marks by mixing up a signal just before an edge with its value just after an edge. Careful time ordering matters more than fast binary arithmetic in most sequential logic problems.