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Diode & Transistor Circuit Builder

Pick a topology, set the supply and component values, and watch the operating point solve in real time. The tool walks the Shockley diode equation, simplified Ebers-Moll BJT, and square-law MOSFET models, then plots the I-V family curves with a live load-line operating point and a switching transfer characteristic.

Circuit

V_supply = 5.00 VR_load1.00k ΩDV_R = 4.308 VV_D = 0.692 VI = 4.31 mA

Controls

V
Ω

Operating Point

Vsupply=IR+VD,I=IS(eVD/(nVT)1)V_{\text{supply}} = I R + V_D, \quad I = I_S\left(e^{V_D / (n V_T)} - 1\right)
V_D
0.6925 V
V_R
4.3075 V
Current I
4.308 mA
Power in device
2.983 mW
Power in resistor
18.555 mW
State
Conducting
V_supply = 5.00 V. Models: ideal Shockley diode, simplified Ebers-Moll BJT, square-law MOSFET. Treat as classroom approximations, not SPICE.

I-V Curve

-0.40.51.42.33.24.15.00.001.202.403.604.806.00V_device (V)I (mA)(0.69, 4.31)

Red dot marks the load-line operating point where the diode's exponential curve meets the resistor's load line.

Reference Guide

Shockley Diode Equation

A pn-junction diode conducts a current that grows exponentially with forward bias and saturates to a tiny reverse current.

I=IS(eVD/(nVT)1)I = I_S\left(e^{V_D / (n V_T)} - 1\right)

Combined with a series resistor R and supply V_supply, the operating point is the intersection of this curve with the load line I = (V_supply - V_D) / R. The tool solves this with Newton iteration.

NPN BJT Regions

A bipolar junction transistor in common-emitter has three regions. Cut-off when V_in is below V_BE ~ 0.7 V. Active when V_in is above the threshold and V_CE stays above V_CE_sat ~ 0.2 V. Saturation when the load resistor cannot drop any more.

IB=VinVBERB,IC=βIBI_B = \frac{V_{\text{in}} - V_{BE}}{R_B}, \quad I_C = \beta\, I_B

In saturation I_C is clamped to (V_supply - V_CE_sat) / R_C, and V_out collapses to a logic-low level near 0.2 V.

MOSFET Square-Law Model

A long-channel NMOS in saturation has a quadratic current. In triode region it depends on V_DS as well.

IDsat=kp2(VGSVth)2I_D^{\text{sat}} = \tfrac{k_p}{2}\,(V_{GS} - V_{th})^2
IDtri=kp[(VGSVth)VDSVDS22]I_D^{\text{tri}} = k_p\left[(V_{GS}-V_{th})\,V_{DS} - \tfrac{V_{DS}^2}{2}\right]

Saturation when V_DS is greater than or equal to V_GS minus V_th, else triode. Below V_th the device is in cut-off.

Switching and Inverters

A common-emitter BJT, an NMOS-with-drain-resistor, and a CMOS pair all invert their input: low V_in gives high V_out and vice versa. The transfer-characteristic plot shows the steep middle region where the device transitions between cut-off and saturation/triode.

CMOS only dissipates short-circuit current during the transition. At V_in = 0 the NMOS is off and V_out = V_supply. At V_in = V_supply the PMOS is off and V_out = 0. In between, both devices conduct briefly.

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